1. Field of the Invention
Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including highly conductive metals, such as copper, embedded into a dielectric material having a low permittivity to enhance device performance.
2. Description of the Related Art
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, also referred to as vias, filled with an appropriate metal. The vias provide electrical connection between two neighboring stacked metallization layers, wherein the metal-containing lines and vias may also be commonly referred to as interconnects.
Due to the continuous shrinkage of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is the packing density, also increases, thereby requiring an even larger increase in the number of electrical interconnections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers entails extremely challenging issues to be solved, such as mechanical, thermal and electrical reliability of a plurality of stacked metallization layers. As the complexity of integrated circuits advances and brings about the necessity for conductive lines that can withstand moderately high current densities, semiconductor manufacturers are increasingly replacing the well-known metallization metal aluminum with a metal that allows higher current densities and hence allows a reduction in the dimensions of the interconnections and thus the number of stacked metallization layers. For example, copper and alloys thereof are materials that are used to increasingly replace aluminum due to their superior characteristics in view of higher resistance against electromigration and significantly lower electrical resistivity when compared with aluminum.
Despite these advantages, copper and copper alloys also exhibit a number of disadvantages regarding the processing and handling in a semiconductor facility. For instance, copper may not be efficiently applied onto a substrate in larger amounts by well-established deposition methods, such as chemical vapor deposition (CVD), and also may not be effectively patterned by the usually employed anisotropic etch procedures. Consequently, in manufacturing metallization layers including copper, the so-called damascene technique (single and dual) is therefore preferably used wherein a dielectric layer is first applied and then patterned to receive trenches and/or vias, which are subsequently filled with copper or copper alloys.
The process of filling copper or copper alloys into highly scaled openings, such as trenches or vias having aspect ratios (depth/diameter) of approximately 5 or even more for sophisticated integrated circuits, is an extremely challenging task for process engineers. As previously noted, copper and its respective alloys may not efficiently be deposited by chemical or physical vapor deposition and hence copper-based metals are typically deposited by electrochemical techniques, such as electroless plating or electroplating. Although electroplating techniques for depositing copper are well established in the field of manufacturing integrated circuit boards, completely new deposition techniques have been developed for the formation of copper-based metallization layers in accordance with the damascene technique regarding the fill behavior during the copper deposition, in which trenches and vias are filled substantially from bottom to top with a minimum number of defects, such as voids within the trenches and vias. After the deposition of the copper or copper-based metal, the excess material deposited on areas outside of the trenches and vias has to be removed, which is currently accomplished by chemical mechanical polishing (CMP), possibly in combination with electrochemical etch techniques. In highly advanced semiconductor devices, the dielectric material, in which the copper-based metal is embedded, typically comprises a so-called low-k material, that is a material having a relative permittivity significantly lower than that of “conventional” dielectric materials, such as silicon dioxide, silicon nitride and the like, so that in general the relative permittivity of the low-k material is 3.0 or even less. However, the reduced permittivity usually comes along with a significantly reduced mechanical strength and stability and different etch properties compared to the standard materials. Therefore, in typical damascene techniques for forming low-k metallization layers of advanced semiconductor devices, a capping layer is provided that ensures the mechanical integrity of the low-k dielectric material, thereby acting as a polish stop layer during the removal of the excess metal.
It turns out that the process of etching vias and trenches in the low-k dielectric layer may significantly affect the overall damascene process flow and may also have an impact on the finally obtained copper-based connection. With reference to FIGS. 1a-1d, a typical conventional process flow will now be described in more detail to more clearly demonstrate the problems involved in forming highly scaled metal lines in a low-k dielectric material.
FIG. 1a schematically shows a cross-sectional view of a semiconductor device 100 comprising a substrate 101, which may be provided in the form of a bulk silicon substrate, a silicon-on-insulator (SOI) substrate and the like, wherein the substrate 101 may also represent a device layer having formed therein individual circuit elements, such as transistors, capacitors, lines, contact portions and the like. For convenience, any such circuit elements are not shown in FIG. 1a. 
The device 100 further comprises a dielectric layer 102 formed above the substrate 101, wherein the layer 102 may represent a dielectric material enclosing the individual circuit elements, or the layer 102 may represent a portion of a lower-lying metallization layer, in which any metal filled vias (not shown) may be embedded. Depending on the specific design of the device 100, or the function of the layer 102, it may be comprised of a conventional dielectric material such as silicon dioxide, silicon nitride, or may comprise a low-k dielectric material such as, for instance, hydrogen-enriched silicon oxycarbide (SiCOH). A metal line 103 is formed above the substrate 101 and at least partially within the layer 102. The metal line 103 may be comprised of a copper-containing metal including conductive barrier layers (not shown) to enhance adhesion of the metal line to the surrounding material and reduce diffusion of copper into sensitive device regions. An etch stop layer 104 is formed on the dielectric layer 102 and the metal line 103, wherein the etch stop layer may be comprised of a material that exhibits a high etch selectivity to the material of a low-k dielectric layer 105 formed on the etch stop layer 104. Furthermore, the etch stop layer 104 typically acts as a diffusion barrier between the metal line 103 and neighboring materials to reduce the out-diffusion of metal, such as copper, and diffusion of dielectric material into the metal line 103. Moreover, the condition of an interface between the etch stop layer 104 and the metal line 103 may significantly affect the electric characteristics of the metal line 103 with respect to electromigration. Frequently, silicon nitride is used as material for the etch stop layer 104, when the moderately high permittivity thereof is considered appropriate for the device 100, whereas silicon carbide or nitrogen-enriched silicon carbide is often used in speed critical applications requiring a low overall permittivity of the layers 105, 104 and 102.
Formed on the low-k dielectric layer 105, which may be comprised of any suitable low-k dielectric, is an ARC layer or capping layer 106, which may be formed from two or more sub-layers to achieve the desired performance with respect to the optical behavior, mechanical strength and masking characteristics. For instance, the capping layer 106 may be formed from a silicon dioxide layer, acting to impart improved mechanical strength to the low-k layer 105, followed by a silicon oxynitride layer for adapting the optical behavior and a thin silicon dioxide layer acting as a nitrogen barrier for a resist mask 107 formed on the capping layer 106.
A typical process flow for forming the semiconductor device 100 as shown in FIG. 1a may comprise the following processes. After the completion of any circuit elements within the substrate 101, the dielectric layer 102 may be deposited by well-established deposition recipes based on plasma enhanced chemical vapor deposition (PECVD). For example, the layer 102 may be comprised of silicon dioxide, fluorine-doped silicon dioxide or SiCOH and, hence, deposition recipes on the basis of appropriate precursors may be employed to form the layer 102. Then, the metal line 103 may be formed in accordance with processes as will be described in the following with reference to the layer 105. Thereafter, the etch stop layer 104 is deposited by, for instance, well-established PECVD with a thickness that is sufficient to reliably stop a via etch process to be performed later on. Next, the low-k dielectric layer 105 is formed by CVD or spin coating, depending on the material used. Then, the capping layer 106 is formed by PECVD techniques on the basis of well-established recipes to provide the desired characteristics in the further processing of the device 100. Finally, the resist mask 107 may be formed by advanced photolithography to form a respective opening 107a, which may represent the dimensions of a via to be formed down to the metal line 103, or a trench as is typically formed as a boundary of a die region, as will be shown in more detail in FIG. 1c. 
FIG. 1b schematically depicts the device 100 with an opening 105a formed in the layer 106, the low-k dielectric layer 105 and partially in the etch stop layer 104. For this purpose, an anisotropic etch process is performed wherein, in an initial phase, the exposed portion of the layer 106 is removed and, in a subsequent process, the low-k dielectric material is removed to form the opening 105a, which in FIG. 1b may represent a via opening, while at the periphery the opening 105a may represent a trench.
FIG. 1b further shows a cross-sectional view of the device 100 at the boundary of a die region, wherein a metal trench is to be formed that separates an inner die region from a so-called open area. Thus, an opening 105b represents a trench that is aligned to a lower metal line 103a. 
It should be noted that the anisotropic etch process is performed to simultaneously form the openings 105a and 105b representing a via opening and a trench, respectively. During this anisotropic process, the initial phase for etching through the layer 106 may require a different etch chemistry compared to the main etch for removing the low-k dielectric material of the layer 105 due to differences in material composition, density and the like. Typically, an etch chemistry on the basis of carbon and fluorine is used during the main etch step, which usually produces fluorine-containing polymers that may deposit on walls of an etch chamber, on the substrate and the like. Moreover, when the etch front reaches the etch stop layer 104, material thereof is also removed, even though at a significantly lower removal rate compared to the material of the layer 105. However, the different kinetic conditions within the via opening 105a and the trench opening 105b, as well as a certain non-uniformity across the entire substrate 101 and from substrate to substrate, require a very high etch selectivity between the etch stop layer 104 and the low-k dielectric layer 105 to reliably stop the etch process without exposing some of the metal lines 103 and 103a to the etch ambient and without necessitating an undue thickness of the etch stop layer 104, which might compromise the overall permittivity of the layer stack. As a consequence, it is very difficult to finely tune a remaining thickness 104a of the layer 104 in the opening 105a and the thickness 104b of the layer 104 in the opening 105b during the anisotropic etch process, thereby contributing to undesired process variations in a subsequent process for etching through the remaining etch stop layer 104 having the reduced thickness 104a and 104b. Next, the resist mask 107 is removed by means of an oxygen plasma.
FIG. 1c schematically illustrates the device 100 in an advanced manufacturing stage at a location on the substrate 101 that relates to the via opening 105a and the trench opening 105b. The device 100 now comprises a resist mask 109 having formed therein a trench 109a above the opening 105a with dimensions corresponding to design dimensions of a trench to be formed around the via opening 105a. The resist mask 109 further comprises a trench 109b formed above the trench opening 105b in accordance with the dimensions thereof. Moreover, a fill material 108 is formed underneath the resist mask 109, wherein the fill material 108 is also provided within the openings 105a and 105b. The fill material may be comprised of a photoresist of different type compared to the resist mask 109, or the fill material 108 may represent any other polymer material that may be applied in a low viscous state to fill the openings 105a and 105b while providing a substantially planar surface. The fill material 108 may also serve as an ARC layer during the patterning of the resist mask 109.
The resist mask 109 may be formed by first applying the fill material 108 by, for example, spin coating a resist or a polymer material and then applying a photoresist by spin coating and performing a well-established photolithography process and etching the fill material 108 on the basis of the resist mask 109. Thereafter, the device 100 is subjected to an etch ambient 110 on the basis of carbon and fluorine to etch through the layer 106 and remove a portion of the layer 105 to form a trench around the via opening 105a while the resist mask 109 and the fill material 108 at the trench opening 105b prevent substantial material removal. Moreover, the fill material 108 within the openings 105a and 105b, although also partially removed during the etch process 110, protects the remaining etch stop layer 104 so that the metal lines 103 and 103a are not exposed to the etch ambient 110. After a trench of specified depth is formed around the via opening 105a, the resist mask 109 and the fill material 108 are removed by, for instance, an oxygen-based plasma treatment.
FIG. 1d schematically shows the device after the above process sequence with a trench 111 formed in the layer 106 and the low-k dielectric layer 105 around the via opening 105a. Moreover, the device is subjected to a further etch process 112 to remove the remaining etch stop layer 104 having the reduced thickness 104a and 104b (FIG. 1b). During the etch process 112 requiring a carbon- and fluorine-based etch recipe, upper portions 111a of the trenches 111 and 105b are permanently exposed to the etch ambient 112, thereby creating a certain amount of edge rounding, which may in many applications be undesirable owing to the risk of trench “bridging” of closely spaced trenches 111 when filled with a metal. As previously pointed out, the remaining etch stop layer 104 has reduced thicknesses 104a and 104b resulting from the etch process performed to form the via opening 105a and trench opening 105b. Hereby, the controllability of the etch process is moderately poor due to different kinematic conditions in the trench 105b and the opening 105a, across-substrate non-uniformities and the like. Consequently, the reduced thicknesses 104a and 104b have to be selected sufficiently high to reliably prevent etching through the etch stop layer 104, thereby damaging the underlying metal lines 103 and 103a. However, the moderately high and not very well-controlled thicknesses 104a and 104b require the etch process 112 to be performed sufficiently long to reliably expose the metal lines 103 and 103a, thereby also causing undue edge rounding at the upper trench portions 111a. 
In view of the situation described above, there exists a need for an improved technique which solves or at least reduces the effects of one or more of the problems identified above.